1. Field of the Invention
The invention relates to host adapter or I/O interface devices and in particular to host adapters connected directly to a host system bus wherein the adapters use DMA controllers adapted to automatically transmit reply messages to requesting host system without intervention from the general purpose processor of the host adapter.
2. Discussion of Related Art
Host computing systems generally include a system bus in which I/O interface circuits are inserted to connect the host system to peripheral I/O devices. Such circuits are often referred to as host adapters, I/O interfaces, I/O processors (IOP) and other equivalent terms and acronyms. The current trend for high-end networking and storage technology pushes more functionality down to the low-level driver, while demanding higher performance. To meet these requirements, hardware vendors are turning to intelligent host adapters that contain their own I/O controller circuits and associated processing capability for processing I/O transactions. RAID controllers for storage and ATM controllers for networking are exemplary of such high performance intelligent host adapters. Intelligent host adapters may include significant local processing power and local memory used for processing of host I/O requests and for control of attached I/O devices. It is therefore known in the art to provide significant processing intelligence within host adapters.
The I2O standards have also become popular in the art as a standardized interconnection between a host system and associated intelligent adapters. The I2O standards are published and maintained by an industry group known as: I2O Special Interest Group; 404 Balboa Street; San Francisco, Calif. 94118, USA (also accessible through the World Wide Web at "http://www.I2Osig.org"). The I2O interface standards define layers of an interface structure between, for example, a host system and an intelligent host adapter. The layers are defined in a symmetric manner such that corresponding layers in each of two communicating nodes essentially communicate with one another via corresponding lower layers.
The standard serves to simplify driver modules by isolating device dependencies in the modules. Driver modules written in conformance with this standard are also more portable among a variety of system architectures. The I2O specification partitions the device driver into a first portion that contains all the OS-specific code and another portion for hardware-specific code unique to a particular class of I/O device. OS vendors need to produce only one OS-specific module for each class of I/O device. Likewise, hardware vendors have to produce only a single version of the hardware device module for an I/O adapter. The device driver can be split more than once, creating stackable drivers. This enables an independent software vendor to support system expansion, independent of both the hardware and the OS.
The corresponding lowest layers in an I2O host system and an I2O intelligent adapter communicate with one another via shared memory data structures. The shared memory is accessible via the common system bus interconnecting the communicating nodes (i.e., the host system and the intelligent adapter). Specifically, the I2O interface defines a number of standard queues and other data structures commonly accessible in memories shared between the respective processors of the host system and the intelligent adapters. The Peripheral Component Interconnect (PCI) bus has become a popular system bus for direct connection of such host adapters to the host system. In such system bus configurations the host system may directly access the local memory of the host adapter. In like manner the host adapter may directly access the memory of the host system. Using such direct access to one another's memory, it is common to use direct memory access (DMA) components in host adapters to perform the requisite transfers of data with minimal overhead imposed on the general purpose processing power of both the host system and the host adapter.
It is also generally known in the art to use scatter/gather DMA techniques to permit flexibility in the distribution of data to be exchanged between a source and destination in a DMA transfer. Such scatter/gather techniques enable a DMA to retrieve data for the transfer from non-contiguous memory locations in the source memory (gather) and/or to store the retrieved data in non-contiguous locations of the destination memory (scatter). As presently known in the art, scatter/gather DMA devices use at least one scatter/gather list that specifies to the DMA transfer circuits (DMA engine) a series of source blocks of data to be retrieved and a corresponding series of destination blocks into which the retrieved data is to be stored.
In general, a host adapter performs I/O operations with the attached I/O peripheral in response to receipt of an I/O request from the host system. Data is generally transferred between the host system memory and the local memory of the host adapter. For example, in processing a write request, the data to be written is transferred from the host system memory to the local memory of the host adapter (via DMA) and then on to the attached I/O device. In processing a read request, the requested data is retrieved or derived from the attached I/O device into the local memory of the host adapter and then transferred from the host adapter local memory to the host system memory (again, via DMA).
In processing of a host I/O request, the host adapter generally constructs a scatter/gather DMA block list to define the entire transfer required between the adapter's local memory and the host system's memory. At completion of processing of the specified scatter/gather list(s) the host adapter's processor is interrupted to complete the I2O specific transaction. For example, the host system may require a response from the I2O compatible host adapter to indicate that the requested transfer is complete and the status of the completion.
As is presently known in the art, the DMA transfer is terminated (completed) at any point in the exchange which may require a response from the adapter to the host system. This completion of the desired transfer is indicated to the processor of the adapter by the DMA completion (e.g., completion interrupt from the DMA controller to the processor). The host adapter's processor then performs requisite data exchanges to generate the required response and to transfer the response to the host system through the I2O interface.
Such a pause or stoppage of a DMA transfer to generate a response and the processor time required for the general purpose processor to construct a desired response can negatively impact overall performance of the storage subsystem. Overall system performance would be enhanced if the processor need not intervene in the DMA transfer or even participate in the generation and transmission of a I2O response. In particular, since a large percentage of DMA operations are completed normally (i.e., without error), normal replies for such normal completions are responsible for the vast majority of such processing overhead within a host adapter.
It can be seen from the above discussion that a need exists for an improved architecture for host adapters to perform DMA operations which are integrated with response generation and transmission.